The general trend in the design of semiconductor devices is packing more computing power into an ever-shrinking feature size. This, however, leads to a number of technical challenges. For example, exponentially rising power consumption leads to power supply voltage scaling. Additionally, for low-power nano-electronics which require 0.4-volt VDD and a ratio of drive current (ION) to leakage current (IOFF) in the order of approximately 106, an average swing of less than 60 mV/dec or a sub-threshold swing (SS) of much less than 60 mV/dec is required as the reduction of SS results in lower power consumption and better performance. However, the theoretical limit for complementary metal oxide (CMOS) technology is 60 mV/dec at room temperature.
Therefore, it is desirable to provide a highly scalable device with increased ION and SS which is less than the theoretical limit of CMOS technology.